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max792/max820 microprocessor and non-volatile memory supervisory circuits ________________________________________________________________ maxim integrated products 1 19-0147; rev. 2; 6/98 general description the max792/max820 microprocessor (?) supervisory circuits provide the most functions for power-supply and watchdog monitoring in systems without battery backup. built-in features include the following: 1) p reset: assertion of reset and reset outputs dur- ing power-up, power-down, and brownout condi- tions. reset is guaranteed valid for v cc down to 1v. 2) manual-reset input. 3) two-stage power-fail warning: a separate low-line comparator compares v cc to a preset threshold 120mv above the reset threshold; the low-line and reset thresholds can be programmed externally. 4) watchdog fault output: assertion of wdo if the watch- dog input is not toggled within a preset timeout period. 5) pulsed watchdog output: advance warning of impending wdo assertion from watchdog timeout that causes hardware shutdown. 6) write protection of cmos ram, eeprom, or other memory devices. the max792 and max820 are identical, except the max820 guarantees higher low-line and reset threshold accuracy (?%). applications computers controllers intelligent instruments critical ? power monitoring features ? manual-reset input ? 200ms power-ok / reset time delay ? independent watchdog timer?reset or adjustable ? on-board gating of chip-enable signals ? memory write-cycle completion ? 10ns (max) chip-enable gate propagation delay ? voltage monitor for overvoltage warning ? ?% reset and low-line threshold accuracy (max820, external programming mode) ordering information continued at end of data sheet. * dice are tested at t a = +25?, dc parameters only. **these parts offer a choice of five different reset threshold volt- ages. select the letter corresponding to the desired nominal reset threshold voltage and insert it into the blank to complete the part number. max792 4 5 7 8 9 1 10 6 14 address decoder reset in/int llin/ refout ovi swt 3 v cc gnd 12 mr reset low line ovo ce in ce out 0.1? v cc ram a0-a15 v cc gnd nmi reset m p 13 typical operating circuit part** temp. range pin-package max792 _cpe 0? to +70? 16 plastic dip max792_cse 0? to +70? 16 narrow so max792_c/d 0? to +70? dice* suffix reset threshold (v) 4.62 4.37 3.06 2.91 2.61 l m t s r for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. ordering information
max792/max820 input voltage (with respect to gnd) v cc .......................................................................-0.3v to +6v all other inputs.......................................-0.3v to (v cc + 0.3v) input current gnd ................................................................................25ma all other outputs ............................................................25ma continuous power dissipation (t a = +70?) plastic dip (derate 10.53mw/? above +70?) ..........842mw narrow so (derate 9.52mw/? above +70?) ............762mw cerdip (derate 10.00mw/? above +70?) ...............800mw operating temperature ranges: max792_c__/max820_c__ ................................0? to +70? max792_e__/max820_e__ .............................-40? to +85? max792_mje__/max820_mje__ ..................-55? to +125? storage temperature range .............................-65? to +160? lead temperature (soldering, 10sec) .............................+300? 2 _______________________________________________________________________________________ microprocessor and non-volatile memory supervisory circuits parameter reset active timeout period conditions max820r, t a = +25?, v cc falling (note 1) 2.55 2.66 min typ max units v cc rising max820s, t a = +25?, v cc falling 2.85 2.96 reset output voltage reset threshold voltage internal threshold mode (v th ) max820t, t a = +25?, v cc falling 3.00 3.11 v 140 200 280 max792, v cc = 5v or v cc = 3v 1.25 1.30 1.35 reset threshold voltage external threshold mode (v th ) max820, v cc = 5v or v cc = 3v 1.274 1.30 1.326 v reset in/ int mode threshold (note 2) internal threshold mode 60 mv reset in/ int leakage current ?.01 ?5 na reset threshold hysteresis 0.016 x v th v reset comparator delay v cc falling 70 ? ms reset output voltage operating voltage range i sink = 50?, v cc = 1v, v cc falling 0.01 0.3 i source = 1ma 2.65 v supply current v cc - 1 i sink = 1.6ma 0.1 0.4 70 150 ? i source = 100? v cc - 0.5 i source = 1ma v cc - 1 v max792l, max820l i source = 100? 4.50 4.62 4.75 v cc - 0.5 v max792m, max820m 4.25 4.37 4.50 max792r, max820r i sink = 1.6ma 2.55 2.61 2.70 0.1 0.4 max792s, max820s 2.85 2.91 3.00 max792t, max820t 3.00 3.06 3.15 max820l, t a = +25?, v cc falling 4.55 4.70 max820m, t a = +25?, v cc falling 4.30 4.45 electrical characteristics (v cc = 2.65v to 5.5v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings reset comparator
max792/max820 _______________________________________________________________________________________ 3 microprocessor and non-volatile memory supervisory circuits electrical characteristics (continued) (v cc = 2.65v to 5.5v, t a = t min to t max , unless otherwise noted.) parameter conditions ms min typ max units ? lowline short-circuit current output source current, v cc = 5.5v 10 50 swt connected to v cc , v cc = 5v 1.00 1.60 2.25 swt connected to v cc , v cc = 3v 1.00 1.60 2.25 4.7nf capacitor connected from swt to gnd , v cc = 3v 70 watchdog timeout period 4.7nf capacitor connected from swt to gnd , v cc = 5v max792/max820l/m 100 sec 50 120 210 low-line threshold voltage (internal threshold mode)? th max792/max820r/s/t v cc = 5v 40 100 210 mv 100 max792, v cc = 5v or v cc = 3v watchdog input pulse width v il = 0v, v ih = v cc 1.25 1.30 1.35 low-line threshold voltage (external programming mode) v cc = 3v max820, v cc = 5v or v cc = 3v 300 ns 1.274 1.30 1.326 v low-line hysteresis (internal threshold mode) i sink = 50?, v cc = 1v, v cc falling 20 mv 0.01 0.30 i sink = 1.6ma 0.1 0.4 i source = 1ma v cc - 1 wdo output voltage i source = 100? v cc - 0.5 v i source = 100? wdpo to wdo delay 70 ns wdpo duration 0.5 1.7 6.0 ms i sink = 50?, v cc = 1v, v cc falling 0.01 0.3 i sink = 1.6ma 0.1 0.4 v ih i source = 1ma v cc - 1 wdpo output voltage v il v cc - 0.5 v v ih 0.75 x v cc v il v cc = 4.25v 0.8 0.9 x v cc wdi threshold voltage v cc = 2.55v 0.2 v wdi input current ? ? llin/refout leakage current external programming mode ?.01 ?5 na low-line comparator delay v cc falling 450 ? i sink = 3.2ma 0.4 lowline voltage i source = 1? v cc - 1 v low-line comparator watchdog function
max792/max820 4 _______________________________________________________________________________________ microprocessor and non-volatile memory supervisory circuits note 1: the minimum operating voltage is 2.65v; however, the device is guaranteed to operate down to its preset reset threshold. note 2: pulling reset in/ int below 60mv selects internal threshold mode and connects the internal voltage divider to the reset and low-line comparators. external programming mode allows an external resistor divider to set the low-line and reset thresholds (see figure 4). note 3: the chip-enable propagation delay is measured from the 50% point at ce in to the 50% point at ce out. parameter conditions v cc = 5v or v cc = 3v min typ max units i sink = 3.2ma i source = 1? output source current, v cc = 5.5v v od = 100mv, ovi rising mr pull-up current v ih 0.75 x v cc mr = 0v v cc = 2.5v v cc = 4.25v v il 0.8 1 v ih 0.75 x v cc ce in threshold voltage v cc = 2.55v v il 0.2 v ce in leakage current 50 source impedance driver, c load = 50pf disabled mode ?.005 ? ? v cc = 5v v cc = 3v v cc = 5v 75 150 610 ce in to ce out resistance ovi input threshold enabled mode v cc = 3v 150 300 1.25 1.30 1.35 v ovi leakage current ?.01 ?5 na v cc = 5v 0.5 2.5 ce out short-circuit current 0.4 ovo output voltage disabled mode, ce out = 0v v cc = 3v 0.05 0.2 0.4 v cc - 1 v ma chip-enable propagation delay (note 3) 10 50 813 ns i out = -100? v cc - 1 chip-enable output voltage high (reset active) i out = 10? v cc - 0.5 v reset active to ce out high v cc falling 15 ? mr minimum pulse width 25 ? mr to reset propagation delay 12 ? mr threshold range 1.1 1.3 1.5 v v cc = 4.25v to v cc = 5.5v 52380 ? ovo short-circuit current ? 13 ovi to ovo delay v od = 100mv, ovi falling 55 ? electrical characteristics (continued) (v cc = 2.65v to 5.5v, t a = t min to t max , unless otherwise noted.) manual reset chip-enable gating overvoltage comparator
max792/max820 microprocessor and non-volatile memory supervisory circuits _________________________________________________________________________________________________ 5 400 -60 low-line comparator propagation delay vs. temperature 100 300 200 max792-3a temperature (?) propagation delay ( m s) 500 600 -30 0 30 60 90 120 150 v cc = 5v v cc = 3v v cc falling 15mv overdrive external programming mode __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.) 80 0 -60 150 supply current vs. temperature 20 60 max792-1 temperature (?) supply current ( m a) 40 10 30 50 70 90 100 -30 0 30 60 90 120 v cc = 2v v cc = 3v v cc = 4v v cc = 5v swt = v cc all outputs unloaded 50 40 -60 overvoltage comparator propagation delay vs. temperature 30 max792-2 temperature (?) propagation delay ( m s) 60 70 -30 0 30 60 90 120 150 v ih to v ol v in = 20mv overdrive = 15mv 40 -60 reset comparator propagation delay vs. temperature 50 max792-3 temperature (?) propagation delay ( m s) 60 70 60 80 -30 0 30 90 120 150 v cc falling 15mv overdrive external programming mode 0 -60 power-up reset delay vs. temperature 100 max792-4 temperature (?) delay (ms) 60 300 200 50 150 250 -30 0 30 90 120 150 1.0 nominal watchdog timeout period vs. v cc max792-5 v cc (v) nominal watchdog timeout period (sec) 4 3.0 2.0 2 3 5 1.5 2.5
max792/max820 microprocessor and non-volatile memory supervisory circuits 6 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) 100k 10 1n 1m watchdog timeout period vs. swt load capacitance 1k 10k max792-10 c swt (f) watchdog timeout period (ms) 10n 100n 100 v cc = 5v v cc = 3v 20 0 0 25 125 250 chip-enable propagation delay vs. ce out load capacitance 5 15 max792-11 c load (pf) propagation delay (ns) 75 200 10 50 100 150 175 225 v cc = +5v v ce in = 0v to 5v driver source impedance = 50 w 1.25 0 120 ref out voltage vs. temperature max792-7 temperature (?) ref out (v) 1.26 1.27 1.28 1.29 1.30 1.31 1.32 1.33 150 90 60 30 -30 -60 reset in / int = 0v 160 20 0 60 120 chip-enable on-resistance vs. temperature 40 120 max792-8 temperature (?) on-resistance ( w ) 80 180 200 60 100 140 90 150 30 -30 -60 v cc = 5v v ce in = 2.5v 0 v cc = 3v v ce in = 1.5v 0.900 0 60 150 internal-mode reset threshold vs. temperature (normalized) max792-6 temperature (?) reset threshold 120 90 30 -30 -60 0.925 0.950 1.000 1.025 1.050 1.075 1.100 1.125 0.975 the reset threshold is shown normalized to 1, representing all available max792/max820
max792/max820 microprocessor and non-volatile memory supervisory circuits _______________________________________________________________________________________ 7 ______________________________________________________________pin description pin name function 1 reset 2 reset reset is the inverse of reset . 3v cc input supply voltage 4 reset in/ int 5 llin/ref out 6 ovo 7 ovi 8 swt 9 mr 10 low line 11 wdi 12 gnd ground 13 ce out active-low reset output goes low whenever v cc falls below the reset threshold in internal thresh- old programming mode, or reset in falls below 1.30v in external threshold programming mode. reset remains low for 200ms typ after the threshold is exceeded on power-up. reset-input/internal-mode select. connect this input to gnd to select internal threshold mode. select external programming mode by pulling this input 600mv or higher through an external volt- age divider. low-line input/reference output connects directly to the low-line comparator in external program- ming mode (reset in/ int 3 600mv). connects directly to the internal 1.30v reference in internal threshold mode (reset in/ int 60mv). overvoltage comparator output goes low when ovi is greater than 1.30v. this is an uncommitted comparator and has no effect on any other internal circuitry. inverting input to the overvoltage comparator. when ovi is greater than 1.30v, ovo goes low. connect ovi to gnd or v cc when not used. set watchdog-timeout input. connect this input to v cc to select the default 1.6sec watchdog timeout period. connect a capacitor between this input and gnd to select another watchdog- timeout period. watchdog timeout period = k x (capacitor value in nf)mv, where k = 27 for v cc = 5v and k = 16.2 for v cc = 3v. if the watchdog function is unused, connect swt to v cc . 16 wdpo 15 wdo 14 ce in manual-reset input. this input can be tied to an external momentary pushbutton switch, or to a logic gate output. internally pulled up to v cc . low-line output. low line goes low 120mv above the reset threshold in internal threshold mode, or when llin/refout goes below 1.30v in external programming mode. watchdog input. if wdi remains either high or low for longer than the watchdog timeout period, wdpo pulses low and wdo goes low. wdo remains low until the next transition at wdi. connect to gnd or v cc if unused. chip-enable output. ce out goes low only when ce in is low and reset is not asserted. if ce in is low when reset is asserted, ce out will stay low for 15? or until ce in goes high, whichever occurs first. chip-enable input?he input to the chip-enable transmission gate. connect to gnd or v cc if not used. watchdog output. wdo goes low if wdi remains either high or low longer than the watchdog time- out period. wdo returns high on the next transition at wdi. watchdog-pulse output. upon the absence of a transition at wdi, wdpo will pulse low for a mini- mum of 500?. wdpo precedes wdo by typically 70ns.
max792/max820 microprocessor and non-volatile memory supervisory circuits 8 _______________________________________________________________________________________ detailed description manual-reset input many ?-based products require manual-reset capabil- ity, allowing the operator to initiate a reset. the manu- al/external-reset input ( mr) ca n connect directly to a switch without an external pull-up resistor or debounc- ing network. mr internally connects to a 1.30v com- parator, and has a high-impedance pull-up to v cc , as shown in figure 1. the propagation delay from assert- ing mr to reset asserted is typically 12?. pulsing mr low for a minimum of 25? asserts the reset function (see reset function section). the reset output remains active as long as mr is held low, and the reset timeout period begins after mr returns high (figure 2). to pro- vide extra noise immunity in high-noise environments, pull mr up to v cc with a 100k resistor. use mr as either a digital logic input or as a second low- line comparator. normal ttl/cmos levels can be wire-or connected via pull-down diodes (figure 3), and open-drain/collector outputs can be wire-ored directly. monitoring the regulated supply the max792/max820 offer two modes for monitoring the regulated supply and providing reset and non- maskable interrupt (nmi) signals to the ?: internal threshold mode uses the factory preset low-line and reset thresholds, and external programming mode allows the low-line and reset thresholds to be pro- grammed externally using a resistor voltage divider (figure 4). internal threshold mode connecting the reset-input/internal-mode select pin (reset in / int ) to ground selects internal threshold mode (figure 4a). in this mode, the low-line and reset thresholds are factory preset by an internal voltage divider (figure 1) to the threshold voltages specified in the electrical characteristics (reset threshold voltage and low-line threshold voltage). connect the low-line output ( low line ) to the ? nmi pin, and connect the active-high reset output (reset) or active-low reset output ( reset ) to the ? reset input pin. additionally, the low-line input/reference-output pin (llin/refout) connects to the internal 1.30v refer- ence in internal threshold mode. buffer llin/refout with a high-impedance buffer to use it with external circuitry. in this mode, when v cc is falling, low line is guaranteed to be asserted prior to reset assertion. external programming mode connecting reset in / int to a voltage above 600mv selects external programming mode. in this mode, the low-line and reset comparators disconnect from the inter- nal voltage divider and connect to llin/refout and reset in / int , respectively (figure 1). this mode allows flexibility in determining where in the operating voltage range the nmi and reset are generated. set the low-line and reset thresholds with an external resistor divider, as in figure 4b or figure 4c. reset typically remains valid for v cc down to 2.5v; reset is guaranteed to be valid with v cc down to 1v. calculate the values for the resistor voltage divider in figure 4b using the following equations: 1) r3 = (1.30 x v cc max)/(v low line x i max ) 2) r2 = [(1.30 x v cc max)/(v reset x i max )] - r3 3) r1 = (v cc max/i max ) - (r2 + r3). first choose the desired maximum current through the voltage divider (i max ) when v cc is at its highest (v cc max). there are two things to consider here. first, i max contributes to the overall supply current for the circuit, so you would generally make it as small as possible. second, i max cannot be too small or leakage currents will adversely affect the programmed threshold voltages; 5a is often appropriate. determine r3 after you have chosen i max . use the value for r3 to determine r2, then use both r2 and r3 to determine r1. for example, to program a 4.75v low-line threshold and a 4.4v reset threshold, first choose i max to be 5? when v cc = 5.5v and substitute into equation 1. r3 = (1.30 x 5.5)/(4.75 x 5e-6) = 301.05k . 301k is the nearest standard 0.1% value. substitute into equation 2: r2 = [(1.30 x 5.5)/(4.4 x 5e-6)] - 301k = 23.95k . the nearest 0.1% resistor value is 23.7k . finally, sub- stitute into equation 3: r1 = (5.5/5e-6) - (23.7k + 301k ) = 775k . the nearest 0.1% value resistor is 787k . determine the actual low-line threshold by rearranging equation 1 and plugging in the standard resistor values. the actual low- line threshold is 4.75v and the actual reset threshold is 4.40v. an additional resistor allows the max792/max820 to monitor the unregulated supply and provide an nmi before the regulated supply begins to fall (figure 4c). both of these thresholds will vary from circuit to circuit with resistor tolerance, reference variation, and compara- tor offset variation. the initial thresholds for each circuit will also vary with temperature due to reference and off- set drift. for highest accuracy, use the max820.
max792/max820 microprocessor and non-volatile memory supervisory circuits _______________________________________________________________________________________ 9 max792 max820 internal/ external mode control chip-enable output control reset generator timebase for reset and watchdog v cc watchdog timer watchdog transition detector overvoltage comparator p n internal external 60mv v cc v cc v cc 1.30v low-line comparator manual reset comparator reset comparator v cc v cc p v cc * 4 5 9 14 8 11 7 6 15 16 13 10 1 2 3 reset reset low line ce out wdpo wdo ovo 12 gnd ovi wdi swt ce in mr llin/ refout reset in/ int v cc * switches are shown in internal threshold mode position figure 1. block diagram
max792/max820 microprocessor and non-volatile memory supervisory circuits 10 ______________________________________________________________________________________ low-line output in internal threshold mode, the low-line comparator monitors v cc with a threshold voltage typically 120mv above the reset threshold, and with 15mv of hysteresis. for normal operation (v cc above the reset threshold), low line is pulled to v cc . use low line to provide an nmi to the ?, as described in the previous section, when v cc begins to fall (figure 4). reset function the max792/max820 provide both reset and reset outputs. the reset and reset outputs ensure that the ? powers up in a known state, and prevent code-exe- cution errors during power-up, power-down, or brownout conditions. the reset function will be asserted during the following conditions: 1) v cc less than the programmed reset threshold. 2) mr less than 1.30v typ. 3) reset remains asserted for 200ms typ after v cc rises above the reset threshold or after mr has exceeded 1.30v typ. when reset is asserted, all the internal counters are reset, the watchdog output ( wdo ) and watchdog-pulse output ( wdpo ) are set high, and the set watchdog-time- out input (swt) is set to (v cc - 0.6v) if it is not already connected to v cc (for internal timeouts). the chip- enable transmission gate is also disabled while reset is asserted; the chip-enable input ( ce in) becomes high impedance and the chip-enable output ( ce out) is pulled up to v cc . mr reset ce in ov ce out 25 m s min 12 m s typ 15 m s typ figure 2. manual-reset timing diagram max792 max820 manual reset other reset sources 9 mr * * * . . . diodes not required on open-drain outputs figure 3. diode "or" connections allow multiple reset sources to connect to mr . max792 12 gnd 3 v cc llin/refout reset reset low line reset in/int 4 5 2 10 1 to m p to m p to m p nmi v in figure 4a. connection for internal threshold mode max792 gnd v cc to m p to m p to m p nmi 2 1 10 reset in/int llin/refout reset reset low line 12 v in r3 = 1.30v x v cc max v low line x i max r2 = 1.30v x v cc max v reset x i max ? r3 r1 = v cc max i max ?(r2 + r3) i max = the maximum desired current through the voltage divided. 3 r3 r2 r1 figure 4b. connection for external threshold programming mode
max792/max820 microprocessor and non-volatile memory supervisory circuits ______________________________________________________________________________________ 11 reset outputs (reset and reset ) the reset output is active low and typically sinks 1.6ma at 0.1v. when deasserted, reset sources 1.6ma at typi- cally v cc - 1.5v. the reset output is the inverse of reset . reset is guaranteed to be valid down to v cc = 1v, and an external 10k pull-down resistor on reset ensures that it will be valid with v cc down to gnd (figure 5). as v cc goes below 1v, the gate drive to the reset output switch reduces accordingly, increasing the r ds(on) and the saturation voltage. the 10k pull-down resistor ensures that the parallel combination of switch plus resistor will be around 10k and the saturation voltage will be below 0.4v while sinking 40?. when using an external pull-down resistor of 10k , the high state for the reset output with v cc = 4.75v is typically 4.60v. overvoltage comparator the overvoltage comparator is an uncommitted com- parator that has no effect on the operation of other chip functions. use this input to provide overvoltage indica- tion by connecting a voltage divider from the input sup- ply, as in figure 6. connect ovi to ground if the overvoltage function is not used. ovo goes low when ovi goes above 1.30v. with ovi below 1.30v, ovo is actively pulled to v cc and can source1?. watchdog function the watchdog monitors ? activity via the watchdog input (wdi). if the ? becomes inactive, wdo and wdpo are asserted. to use the watchdog function, connect wdi to a ? bus line or i/o line. if wdi remains high or low for longer than the watchdog timeout period (1.6sec nominal), wdpo and wdo are asserted, indicat- ing a software fault condition (see watchdog-pulse output and watchdog output sections). watchdog input if the watchdog function is unused, connect wdi to v cc or gnd. a change of state (high-to-low, low-to-high, or a minimum 100ns pulse) at wdi during the watchdog period resets the watchdog timer. the watchdog timer max792 max820 gnd v cc regulator r1 r2 r3 r4 to m p to m p to m p nmi 2 1 10 reset in/int llin/refout reset reset low line v low line = 1.3 r1 + r2 r2 ) ( v reset = 1.3 r3 + r4 r4 ) ( figure 4c. alternative connection for external programming mode reset max792 max820 to m p reset 1 10k figure 5. adding an external pull-down resistor ensures reset is valid with v cc down to gnd. max792 max820 6 7 12 gnd 3 v cc ovi ovo overvoltage voltage regulator 1.30v figure 6. detecting an overvoltage condition
max792/max820 microprocessor and non-volatile memory supervisory circuits 12 ______________________________________________________________________________________ default is 1.6sec. select alternative timeout periods by connecting an external capacitor from swt to gnd (see selecting an alternative watchdog timeout sec- tion). when v cc is below the reset threshold, the watch- dog function is disabled. watchdog output wdo remains high if there is a transition or pulse at wdi during the watchdog timeout period. the watchdog function is disabled and wdo is a logic high when v cc is below the reset threshold. if a system reset is desired on every watchdog fault, simply diode-or connect wdo to mr (figure 8). when a watchdog fault occurs in this mode, wdo goes low, pulling mr low and causing a reset pulse to be issued. as soon as reset is asserted, the watchdog timer clears and wdo goes high. with wdo connected to mr , a continuous high or low on wdi will cause 200ms reset pulses to be issued every 1.6sec (swt connected to v cc ). when reset is not asserted, if no transition occurs at wdi during the watchdog timeout period, wdo goes low 70ns after the falling edge of wdpo and remains low until the next tran- sition at wdi (figure 7). a single additional flip- flop can force the system into a hardware shutdown if there are two successive watchdog faults (figure 8). when the max792/max820 are operated from a 5v supply, wdo has a 2 x ttl output characteristic. watchdog-pulse output as described in the preceding section, wdpo can be used as the clock input to an external d flip-flop. upon the absence of a watchdog edge or pulse at wdi at the end of a watchdog timeout period, wdpo will pulse low for 1.7ms. the falling edge of wdpo precedes wdo by 70ns. since wdo is high when wdpo goes low, the flip- flop? q output remains high after wdo goes low (figure 8). if the watchdog timer is not reset by a transition at wdi, wdo remains low and the next wdpo following a second watchdog timeout period clocks a logic low to the q output, pulling mr low and causing the max792/max820 latch in reset. if the watchdog timer is reset by a transition at wdi, wdo will go high and the flip-flop? q output will remain high. thus a system shutdown is only caused by two successive watchdog faults. selecting an alternative watchdog timeout period the swt input controls the watchdog timeout period. connecting swt to v cc selects the internal 1.6sec watchdog timeout period. select an alternative watch- dog timeout period by connecting a capacitor between swt and gnd. do not leave swt floating and do not connect it to ground. the following formula determines the watchdog timeout period: watchdog timeout period = k x (capacitor value in nf)ms where k = 27 for v cc = 3v, and k = 16.2 for v cc = 5v. this applies for capacitor values in excess of 4.7nf. if the watchdog function is unused, connect swt to v cc . wdpo wdo wdi 70ns 1.6sec min 100ns (v cc = 5v) min 300ns (v cc = 3v) v cc = 5v figure 7. wdi, wdo and wdpo timing diagram max792 max820 * for system reset on every watchdog fault, omit the flip-flop, and diode?r connect wdo to mr. 12 gnd 3 v cc v cc 0.1 m f 9 mr 4.7k +5v 1 reset 0.1 m f 11 wdi 16 wdpo 15 wdo m p power v cc reset i/o d clock clear q q v cc two consecutive watchdog fault indication reactivate * figure 8. two consecutive watchdog faults latch the system in reset.
max792/max820 microprocessor and non-volatile memory supervisory circuits ______________________________________________________________________________________ 13 chip-enable signal gating the max792/max820 provide internal gating of chip- enable (ce) signals, which prevents erroneous data from corrupting cmos ram in the event of an under- voltage condition. the max792/max820 use a series transmission gate from ce in to ce out (figure 1). during normal operation (reset not asserted), the ce transmission gate is enabled and passes all ce transi- tions. when reset is asserted, this path becomes dis- abled, preventing erroneous data from corrupting the cmos ram. the 10ns max ce propagation delay from ce in to ce out enables the max792/max820 to be used with most ?s. if ce in is low when reset asserts, ce out remains low for a short period to permit com- pletion of the current write cycle. chip-enable input the ce transmission gate is disabled and ce in is high impedance (disabled mode) while reset is asserted. during a power-down sequence when v cc passes the reset threshold, the ce transmission gate disables and ce in immediately becomes high impedance if the volt- age at ce in is high. if ce in is low when reset is assert- ed, the ce transmission gate will disable at the moment ce in goes high or 15? after reset is asserted, whichever occurs first (figure 9). this permits the cur- rent write cycle to complete during power-down. during a power-up sequence, the ce transmission gate remains disabled and ce in remains high impedance regardless of ce in activity, until reset is deasserted fol- lowing the reset timeout period. while disabled, ce in is high impedance. when the ce transmission gate is enabled, the impedance of ce in will appear as a 75 (v cc = 5v) resistor in series with the load at ce out. the propagation delay through the ce transmission gate depends on v cc, the source impedance of the drive connected to ce in, and the loading on ce out (see the chip-enable propagation delay vs. ce out load capacitance graph in the typical operating characteristics ). the ce propagation delay is produc- tion tested from the 50% point on ce in to the 50% point on ce out using a 50 driver and 50pf of load capacitance (figure 10). for minimum propagation delay, minimize the capacitive load at ce out, and use a low-output-impedance driver. chip-enable output when the ce transmission gate is enabled, the imped- ance of ce out is equivalent to 75 in series with the source driving ce in. in the disabled mode, the 75 transmission gate is off and an active pull-up connects from ce out to v cc . this source turns off when the transmission gate is enabled. applications information connect a 0.1? ceramic capacitor from v cc to gnd, as close to the device pins as possible. this reduces the probability of resets due to high-frequency power- supply transients. in a high-noise environment, addi- tional bypass capacitance from v cc to ground may be required. if long leads connect to the chip inputs, ensure that these lines are free from ringing, etc., which would forward bias the chip? protection diodes. v cc ce in reset threshold ce out reset reset 70 m s 15 m s 70 m s figure 9. reset and chip-enable timing max792 max820 50 w driver 13 14 12 +5v gnd c load 3 v cc ce in ce out figure 10. ce propagation delay test circuit
max792/max820 microprocessor and non-volatile memory supervisory circuits 14 ______________________________________________________________________________________ alternative chip-enable gating using memory devices with both ce and ce inputs allows the max792/max820 ce propagation delay to be bypassed. to do this, connect ce in to ground, pull up ce out to v cc , and connect ce out to the ce input of each memory device (figure 11). the ce input of each memory device then connects directly to the chip-select logic, which does not have to be gated by the max792/max820. interfacing to ?s with bidirectional reset inputs ?s with bidirectional reset pins, such as the motorola 68hc11 series, can contend with the max792/max820 reset output. if, for example, the max792/max820 reset output is asserted high and the ? wants to pull it low, indeterminate logic levels may result. to avoid this, connect a 4.7k resistor between the max792/max820 reset output and the ? reset i/o, as in figure 12. buffer the max792/max820 reset output to other sys- tem components. negative-going v cc transients while issuing resets to the ? during power-up, power- down, and brownout conditions, these supervisors are relatively immune to short-duration negative-going v cc transients (glitches). it is usually undesirable to reset the ? when v cc experiences only small glitches. figure 13 shows maximum transient duration vs. reset- comparator overdrive, for which reset pulses are not generated. the graph was produced using negative- going v cc pulses, starting at 5v and ending below the reset threshold by the magnitude indicated (reset- comparator overdrive). the graph shows the maximum pulse width a negative-going v cc transient may typi- cally have without causing a reset pulse to be issued. as the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allow- able pulse width decreases. typically, a v cc transient that goes 100mv below the reset threshold and lasts for 30? or less will not cause a reset pulse to be issued. a 100nf bypass capacitor mounted close to the v cc pin provides additional transient immunity. max792 max820 13 14 12 +5v gnd 3 v cc ce in ce out ce ce ce ce ce ce ce ce ram 1 ram 2 ram 3 ram 4 active-high ce lines from logic maximum r p value depends on the number of rams. minimum r p value is 1k w * r p * figure 11. alternate ce gating v cc v cc v cc buffer to other system reset inputs 4.7k 1 reset reset gnd gnd 12 max792 max820 m p 3 figure 12. interfacing to ?s with bidirectional reset pins figure 13. maximum transient duration without causing a reset pulse vs. reset-comparator overdrive 100 0 10 100 10,000 40 20 80 60 max791 -13 reset comparator overdrive, (v th - v cc ) (mv) maximum transient duration (?) 1000 v cc = 5v t a = +25?
suffix reset threshold (v) l m t s r 4.62 4.37 3.06 2.91 2.61 max792/max820 microprocessor and non-volatile memory supervisory circuits ______________________________________________________________________________________ 15 _ordering information (continued) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 wdpo wdo ce in ce out reset in/int v cc reset reset top view max792 max820 gnd wdi low line mr swt ovi ovo llin/refout dip/so pin configuration * dice are tested at t a = +25?. **these parts offer a choice of five different reset threshold volt- ages. select the letter corresponding to the desired nominal reset threshold voltage and insert it into the blank to complete the part number. part** temp. range pin-package max792_epe -40? to +85? 16 plastic dip max792_ese -40? to +85? 16 narrow so max792_eje -40? to +85? 16 cerdip max792_mje -55? to +125? 16 cerdip max820 _cpe -0? to +70? 16 plastic dip max820_cse -0? to +70? 16 narrow so max820_epe -40? to +85? 16 plastic dip max820_ese -40? to +85? 16 narrow so max820_eje -40? to +85? 16 cerdip max820_mje -55? to +125? 16 cerdip mr swt ovi 0.078" (1.981mm) 0.070" (1.778mm) reset in/ int llin/ ref out ovo low line wdi gnd ce out reset reset wdpo wdo v cc ce in ___________________chip topography transistor count: 950 substrate connected to v cc
max792/max820 microprocessor and non-volatile memory supervisory circuits ________________________________________________________package information maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1998 maxim integrated products printed usa is a registered trademark of maxim integrated products. soicn.eps soicw.eps

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